Pin Configuration

Pinout table

The Ethernet FMC has a low pin count FPGA Mezzanine Card (FMC) connector, providing the connections to the FPGA on the development board. The following table defines the pinout of the FMC connector and applies to both the Ethernet FMC and the Robust Ethernet FMC.

Pin

Pin name

Net

Description

C1

GND

GND

Ground

C2

DP0_C2M_P

DP0_C2M_P

Not used

C3

DP0_C2M_N

DP0_C2M_N

Not used

C4

GND

GND

Ground

C5

GND

GND

Ground

C6

DP0_M2C_P

DP0_M2C_P

Not used

C7

DP0_M2C_N

DP0_M2C_N

Not used

C8

GND

GND

Ground

C9

GND

GND

Ground

C10

LA06_P

E1_RXD0

Port 1 RGMII Receive Data Bit 0 (PHY-to-FPGA)

C11

LA06_N

E0_MDIO

Port 0 MDIO Data (bidirectional)

C12

GND

GND

Ground

C13

GND

GND

Ground

C14

LA10_P

N/C

Not used

C15

LA10_N

E1_RXD2

Port 1 RGMII Receive Data Bit 2 (PHY-to-FPGA)

C16

GND

GND

Ground

C17

GND

GND

Ground

C18

LA14_P

REF_CLK_FSEL

Reserved

C19

LA14_N

E1_MDIO

Port 1 MDIO Data (bidirectional)

C20

GND

GND

Ground

C21

GND

GND

Ground

C22

LA18_P_CC

E3_RX_CLK

Port 3 RGMII Receive Clock (PHY-to-FPGA)

C23

LA18_N_CC

E3_RX_CTRL

Port 3 RGMII Receive Control (PHY-to-FPGA)

C24

GND

GND

Ground

C25

GND

GND

Ground

C26

LA27_P

E3_RXD1

Port 3 RGMII Receive Data Bit 1 (PHY-to-FPGA)

C27

LA27_N

E3_RXD3

Port 3 RGMII Receive Data Bit 3 (PHY-to-FPGA)

C28

GND

GND

Ground

C29

GND

GND

Ground

C30

SCL

I2C_SCL

I2C Clock (FPGA-to-PHY)

C31

SDA

I2C_SDA

I2C Data (bidirectional)

C32

GND

GND

Ground

C33

GND

GND

Ground

C34

GA0

GA0

EEPROM Address Bit 1 (A1)

C35

12P0V_1

12V0

12VDC (Not used)

C36

GND

GND

Ground

C37

12P0V_2

12V0

12VDC (Not used)

C38

GND

GND

Ground

C39

3P3V_1

3V3

3.3VDC

C40

GND

GND

Ground

D1

PG_C2M

PG

Power Good (Driven by carrier)

D2

GND

GND

Ground

D3

GND

GND

Ground

D4

GBTCLK0_M2C_P

N/C

Not used

D5

GBTCLK0_M2C_N

N/C

Not used

D6

GND

GND

Ground

D7

GND

GND

Ground

D8

LA01_P_CC

E1_RX_CLK

Port 1 RGMII Receive Clock (PHY-to-FPGA)

D9

LA01_N_CC

E1_RX_CTRL

Port 1 RGMII Receive Control (PHY-to-FPGA)

D10

GND

GND

Ground

D11

LA05_P

E0_MDC

Port 0 MDIO Clock (FPGA-to-PHY)

D12

LA05_N

E0_RESET_N

Port 0 PHY Reset (Active-Low)

D13

GND

GND

Ground

D14

LA09_P

E1_RXD1

Port 1 RGMII Receive Data Bit 1 (PHY-to-FPGA)

D15

LA09_N

E1_RXD3

Port 1 RGMII Receive Data Bit 3 (PHY-to-FPGA)

D16

GND

GND

Ground

D17

LA13_P

REF_CLK_OE

Enable LVDS 125MHz Clock (Active-High, enabled by default with pull-up)

D18

LA13_N

E1_MDC

Port 1 MDIO Clock (FPGA-to-PHY)

D19

GND

GND

Ground

D20

LA17_P_CC

E2_RX_CLK

Port 2 RGMII Receive Clock (PHY-to-FPGA)

D21

LA17_N_CC

N/C

Not used

D22

GND

GND

Ground

D23

LA23_P

E2_RXD2

Port 2 RGMII Receive Data Bit 2 (PHY-to-FPGA)

D24

LA23_N

E2_RXD3

Port 2 RGMII Receive Data Bit 3 (PHY-to-FPGA)

D25

GND

GND

Ground

D26

LA26_P

E3_RXD0

Port 3 RGMII Receive Data Bit 0 (PHY-to-FPGA)

D27

LA26_N

E3_RXD2

Port 3 RGMII Receive Data Bit 2 (PHY-to-FPGA)

D28

GND

GND

Ground

D29

TCK

N/C

Not used

D30

TDI

TDI-TDO

JTAG TDI (Connects to TDO to close JTAG chain)

D31

TDO

TDI-TDO

JTAG TDO (Connects to TDI to close JTAG chain)

D32

3P3VAUX

N/C

Not used

D33

TMS

N/C

Not used

D34

TRST_L

N/C

Not used

D35

GA1

GA1

EEPROM Address Bit 0 (A0)

D36

3P3V_2

3V3

3.3VDC

D37

GND

GND

Ground

D38

3P3V_3

3V3

3.3VDC

D39

GND

GND

Ground

D40

3P3V_4

3V3

3.3VDC

G1

GND

GND

Ground

G2

CLK1_M2C_P

N/C

Not used

G3

CLK1_M2C_N

N/C

Not used

G4

GND

GND

Ground

G5

GND

GND

Ground

G6

LA00_P_CC

E0_RX_CLK

Port 0 RGMII Receive Clock (PHY-to-FPGA)

G7

LA00_N_CC

E0_RX_CTRL

Port 0 RGMII Receive Control (PHY-to-FPGA)

G8

GND

GND

Ground

G9

LA03_P

E0_RXD2

Port 0 RGMII Receive Data Bit 2 (PHY-to-FPGA)

G10

LA03_N

E0_RXD3

Port 0 RGMII Receive Data Bit 3 (PHY-to-FPGA)

G11

GND

GND

Ground

G12

LA08_P

E0_TXD1

Port 0 RGMII Transmit Data Bit 1 (FPGA-to-PHY)

G13

LA08_N

E0_TXD2

Port 0 RGMII Transmit Data Bit 2 (FPGA-to-PHY)

G14

GND

GND

Ground

G15

LA12_P

N/C

Not used

G16

LA12_N

E1_TXD0

Port 1 RGMII Transmit Data Bit 0 (FPGA-to-PHY)

G17

GND

GND

Ground

G18

LA16_P

E1_TXD2

Port 1 RGMII Transmit Data Bit 2 (FPGA-to-PHY)

G19

LA16_N

E1_TXD3

Port 1 RGMII Transmit Data Bit 3 (FPGA-to-PHY)

G20

GND

GND

Ground

G21

LA20_P

E2_RX_CTRL

Port 2 RGMII Receive Control (PHY-to-FPGA)

G22

LA20_N

E2_RXD0

Port 2 RGMII Receive Data Bit 0 (PHY-to-FPGA)

G23

GND

GND

Ground

G24

LA22_P

E2_TXD1

Port 2 RGMII Transmit Data Bit 1 (FPGA-to-PHY)

G25

LA22_N

E2_TXD2

Port 2 RGMII Transmit Data Bit 2 (FPGA-to-PHY)

G26

GND

GND

Ground

G27

LA25_P

E2_TX_CTRL

Port 2 RGMII Transmit Control (FPGA-to-PHY)

G28

LA25_N

E2_MDIO

Port 2 MDIO Data (bidirectional)

G29

GND

GND

Ground

G30

LA29_P

N/C

Not used

G31

LA29_N

E3_TXD0

Port 3 RGMII Transmit Data Bit 0 (FPGA-to-PHY)

G32

GND

GND

Ground

G33

LA31_P

E3_TXD2

Port 3 RGMII Transmit Data Bit 2 (FPGA-to-PHY)

G34

LA31_N

E3_TXD3

Port 3 RGMII Transmit Data Bit 3 (FPGA-to-PHY)

G35

GND

GND

Ground

G36

LA33_P

N/C

Not used

G37

LA33_N

N/C

Not used

G38

GND

GND

Ground

G39

VADJ_3

VADJ

I/O Supply Voltage (1.8VDC or 2.5VDC)

G40

GND

GND

Ground

H1

VREF_A_M2C

N/C

Not used

H2

PRSNT_M2C_L

GND

Ground

H3

GND

GND

Ground

H4

CLK0_M2C_P

REF_CLK_P

LVDS 125MHz Precision Clock to FPGA

H5

CLK0_M2C_N

REF_CLK_N

LVDS 125MHz Precision Clock to FPGA

H6

GND

GND

Ground

H7

LA02_P

E0_RXD0

Port 0 RGMII Receive Data Bit 0 (PHY-to-FPGA)

H8

LA02_N

E0_RXD1

Port 0 RGMII Receive Data Bit 1 (PHY-to-FPGA)

H9

GND

GND

Ground

H10

LA04_P

E0_TXD0

Port 0 RGMII Transmit Data Bit 0 (FPGA-to-PHY)

H11

LA04_N

E0_TX_CLK

Port 0 RGMII Transmit Clock (FPGA-to-PHY)

H12

GND

GND

Ground

H13

LA07_P

E0_TXD3

Port 0 RGMII Transmit Data Bit 3 (FPGA-to-PHY)

H14

LA07_N

E0_TX_CTRL

Port 0 RGMII Transmit Control (FPGA-to-PHY)

H15

GND

GND

Ground

H16

LA11_P

E1_TXD1

Port 1 RGMII Transmit Data Bit 1 (FPGA-to-PHY)

H17

LA11_N

E1_TX_CLK

Port 1 RGMII Transmit Clock (FPGA-to-PHY)

H18

GND

GND

Ground

H19

LA15_P

E1_TX_CTRL

Port 1 RGMII Transmit Control (FPGA-to-PHY)

H20

LA15_N

E1_RESET_N

Port 1 PHY Reset (Active-Low)

H21

GND

GND

Ground

H22

LA19_P

E2_RXD1

Port 2 RGMII Receive Data Bit 1 (PHY-to-FPGA)

H23

LA19_N

E2_TXD0

Port 2 RGMII Transmit Data Bit 0 (FPGA-to-PHY)

H24

GND

GND

Ground

H25

LA21_P

E2_TX_CLK

Port 2 RGMII Transmit Clock (FPGA-to-PHY)

H26

LA21_N

E2_TXD3

Port 2 RGMII Transmit Data Bit 3 (FPGA-to-PHY)

H27

GND

GND

Ground

H28

LA24_P

E2_MDC

Port 2 MDIO Clock (FPGA-to-PHY)

H29

LA24_N

E2_RESET_N

Port 2 PHY Reset (Active-Low)

H30

GND

GND

Ground

H31

LA28_P

E3_TXD1

Port 3 RGMII Transmit Data Bit 1 (FPGA-to-PHY)

H32

LA28_N

E3_TX_CLK

Port 3 RGMII Transmit Clock (FPGA-to-PHY)

H33

GND

GND

Ground

H34

LA30_P

E3_TX_CTRL

Port 3 RGMII Transmit Control (FPGA-to-PHY)

H35

LA30_N

E3_MDC

Port 3 MDIO Clock (FPGA-to-PHY)

H36

GND

GND

Ground

H37

LA32_P

E3_MDIO

Port 3 MDIO Data (bidirectional)

H38

LA32_N

E3_RESET_N

Port 3 PHY Reset (Active-Low)

H39

GND

GND

Ground

H40

VADJ_4

VADJ

I/O Supply Voltage (1.8VDC or 2.5VDC)

Net lengths

The table below lists the trace lengths.

Net

Length (mils)

Port 0

E0_TXD0

935.369

E0_TXD1

1022.274

E0_TXD2

1016.451

E0_TXD3

973.815

E0_TX_CLK

926.463

E0_TX_CTRL

1025.089

E0_RXD0

987.273

E0_RXD1

1034.127

E0_RXD2

1066.126

E0_RXD3

989.16

E0_RX_CLK

1055.744

E0_RX_CTRL

1018.718

Port 1

E1_TXD0

821.649

E1_TXD1

781.117

E1_TXD2

830.455

E1_TXD3

867.309

E1_TX_CLK

767.898

E1_TX_CTRL

847.395

E1_RXD0

1336.123

E1_RXD1

1345.882

E1_RXD2

1336.42

E1_RXD3

1296.088

E1_RX_CLK

1262.112

E1_RX_CTRL

1277.099

Port 2

E2_TXD0

910.149

E2_TXD1

902.087

E2_TXD2

922.798

E2_TXD3

882.68

E2_TX_CLK

895.55

E2_TX_CTRL

968.80

E2_RXD0

1106.905

E2_RXD1

1133.374

E2_RXD2

1165.735

E2_RXD3

1169.388

E2_RX_CLK

1105.029

E2_RX_CTRL

1143.103

Port 3

E3_TXD0

1046.468

E3_TXD1

983.755

E3_TXD2

1062.666

E3_TXD3

1075.708

E3_TX_CLK

995.204

E3_TX_CTRL

1056.065

E3_RXD0

1535.853

E3_RXD1

1502.359

E3_RXD2

1499.971

E3_RXD3

1590.42

E3_RX_CLK

1512.856

E3_RX_CTRL

1545.37