Example designs

Quad-port Ethernet using Zynq GEM

Uses the hard Gigabit Ethernet MACs (GEMs) internal to the Zynq PS.

 

Supported FPGA boards:

Requirements:

Source code

Quad-port Ethernet using AXI Ethernet Subsystem

Uses 4 x AXI Ethernet Subsystem IP cores.

Supported FPGA boards:

 

Requirements:

Source code

Maximum Throughput Test

Uses 4 x AXI Ethernet IP cores and 4 x Ethernet packet generators for testing the Ethernet FMC at maximum throughput. The packet generators, designed in Vivado HLS (high-level synthesis) and written in C++, drive the AXI Ethernet cores with a continuous stream of packets, as well as checking the received packets for bit errors. The software application polls the MACs to detect any dropped packets.

See maximum throughput measurements here.

Supported FPGA boards:

 

Requirements:

Source code