Example designs

Quad-port Ethernet using Zynq GEM

Uses the hard Gigabit Ethernet MACs (GEMs) internal to the Zynq PS. For Zynq boards, we use one GEM and 3x AXI Ethernet IPs (see image). For Zynq US+ boards, we use 4x GEMs.

Supported FPGA boards:

Supports only Zynq and Zynq US+ boards. Checkout the Github page for this example design for the most recent list of supported boards. 

 

Requirements:

Quad-port Ethernet using AXI Ethernet Subsystem

Uses 4 x AXI Ethernet Subsystem IP cores. Also has 8x port designs where 2x Ethernet FMCs can be used on the same dev board.

Supported FPGA boards:

Supports Zynq, Zynq US+ and pure FPGA boards. See the Github page for this example design for the latest list of supported boards.

 

Requirements:

Maximum Throughput Test

Uses 4 x AXI Ethernet IP cores and 4 x Ethernet packet generators for testing the Ethernet FMC at maximum throughput. The packet generators, designed in Vivado HLS (high-level synthesis) and written in C++, drive the AXI Ethernet cores with a continuous stream of packets, as well as checking the received packets for bit errors. The software application polls the MACs to detect any dropped packets.

See maximum throughput measurements here.

Supported FPGA boards:

See the Github page for this example design for the latest list of supported boards.

 

Requirements: