Example designs
Quad-port Ethernet using Zynq GEM
Uses the hard Gigabit Ethernet MACs (GEMs) internal to the Zynq PS.
Supported FPGA boards:
- Zynq-7000 ZedBoard
- Zynq-7000 MicroZed 7010/20 requires Robust version Ethernet FMC and MicroZed FMC Carrier
- Zynq UltraScale+ ZCU102 Evaluation Board
Requirements:
- Ethernet FMC
- Vivado & SDK
- Xilinx Soft TEMAC license for designs with AXI Ethernet
Quad-port Ethernet using AXI Ethernet Subsystem
Uses 4 x AXI Ethernet Subsystem IP cores.
Supported FPGA boards:
- Zynq-7000 ZedBoard
- Zynq-7000 PicoZed FMC Carrier Card V2 and PicoZed 7010/15/20/30
- Artix-7 AC701 Evaluation Board
- Kintex-7 KC705 Evaluation Board
- Virtex-7 VC707 Evaluation Board
- Virtex-7 VC709 Evaluation Board
- Zynq-7000 ZC702 Evaluation Board
- Zynq-7000 ZC706 Evaluation Board
- Kintex UltraScale KCU105 Evaluation Board
- Zynq UltraScale+ ZCU102 Evaluation Board
Requirements:
Maximum Throughput Test
Uses 4 x AXI Ethernet IP cores and 4 x Ethernet packet generators for testing the Ethernet FMC at maximum throughput. The packet generators, designed in Vivado HLS (high-level synthesis) and written in C++, drive the AXI Ethernet cores with a continuous stream of packets, as well as checking the received packets for bit errors. The software application polls the MACs to detect any dropped packets.
See maximum throughput measurements here.
Supported FPGA boards: