Using the 1.8V version with the ZedBoard

and other carriers that route to HR (high-range) I/Os

What is the problem?

Some FMC carriers such as the ZedBoard, AC701, KC705, ZC702 and ZC706 have FMC connectors that route to HR (high-range) I/Os. Although HR I/Os can be operated from 1.2V to 3.3V, when it comes to LVDS they are actually limited to the I/O standard LVDS_25 (according to UG471).

The Ethernet FMC has a 125MHz clock which is routed to the FMC connector as an LVDS signal in compliance with the Vita standard. On the aforementioned carriers, this signal is received by the FPGA on a HR bank and therefore must be defined in your Vivado design as LVDS_25.

What if I don’t need the 125MHz clock?

 

Great! If you can supply the 125MHz MAC clock from another source, there is absolutely no problem, because your Vivado design doesn’t need to define the received clock.

 

What if I need the clock?

If you do need the 125MHz clock, you have two options:

  1. Switch to the 2.5V Ethernet FMC, or
  2. Add a 100 ohm external termination resistor to the FPGA input pins that receive the 125MHz LVDS clock signal

The ZedBoard, AC701, KC705, ZC702 and ZC706 do not have external termination resistors on this clock signal, and very few FPGA boards are designed this way because the internal termination resistor creates much better signal integrity. So option 2 really only applies if you are designing your own custom FPGA board, but if that’s the case for you, follow on for the work around:

If you have an external termination resistor on your FPGA board, then you will be able to follow these steps to use the 1.8V Ethernet FMC’s 125MHz clock with the HR I/O routed FMC carriers:

  1. Define the clock in your Vivado design using the IOSTANDARD: LVDS_25.
  2. Define the other FMC I/Os using the IOSTANDARD: LVCMOS_25 (we are required to use 2.5V standards on the entire bank).
  3. Configure your carrier to power VADJ at 1.8V.

In other words, your Vivado design must be configured for VADJ of 2.5V but you will actually power VADJ at 1.8V. This is a valid work-around which is described by answer record 43989, with the limitation that an external termination resistor be used. The reason that you need an external termination resistor is that the circuit for producing the internal termination resistor expects a power supply that corresponds to the IOSTANDARDs defined in the Vivado design. According to answer record 43989, it is prohibited to enable the internal differential termination resistor (DIFF_TERM=TRUE) if you configure your design for one supply voltage and power the I/O banks at another.

WARNING: Never apply 2.5V to the 1.8V version Ethernet FMC, regardless of your Vivado design configuration. Using VADJ above the rated voltage may damage the device.

Here’s why it works

 

Configuring an I/O bank at one voltage and supplying it with a different voltage is a workaround proposed by the following answer record:

http://www.xilinx.com/support/answers/43989.html

Following the flow chart in the answer record for these conditions:

  • LVDS_25 HR bank
  • Input (we only need the clock inputs to be LVDS)
  • VCCO != 2.5V

We get a VIN requirement of:

TxVOCM + TxVOD/2 < VCCO + 0.2V

Now, according to the datasheet of the clock oscillator:

Vod (magnitude of the differential voltage) = 450mV (worst case)
Vocm (common mode voltage) = (1600 + 900)/2 = 1250mV (worst case)

By plugging these values into the above condition, using VCCO = 1.8, we can confirm that the VIN requirement is indeed satisfied.