Compatible Boards

This section of the documentation aims to list all of the development boards for which compatibility with the Ethernet FMC Max has been checked, and to list constraints and any notes concerning special requirements or limitations with the board.

List of boards

The following development boards have been verified compatible with the Ethernet FMC Max. For more detailed information regarding compatibility with a particular development board, including the availability of an example design, click on the name of the board in the table below.

Note that we are still working on the reference designs for these boards and we expect them to be available by September 2024.

Series-7 boards

CarrierFMCCompatibleRef designSupported Ports
AMD Xilinx KC705 Kintex-7 Development boardHPC✔️Coming soon4
AMD Xilinx KC705 Kintex-7 Development boardLPC✔️No1 1
AMD Xilinx VC707 Virtex-7 Development boardHPC1✔️Coming soon4
AMD Xilinx VC707 Virtex-7 Development boardHPC2✔️Coming soon4
AMD Xilinx VC709 Virtex-7 Development boardHPC✔️Coming soon4
AMD Xilinx ZC706 Zynq-7000 Development boardHPC✔️Coming soon4
AMD Xilinx ZC706 Zynq-7000 Development boardLPC✔️No1 1
Avnet PicoZed FMC Carrier Card V2 Zynq-7000 Development BoardLPC✔️No1 1

UltraScale boards

CarrierFMCCompatibleRef designSupported Ports
AMD Xilinx KCU105 Kintex UltraScale Development boardHPC✔️Coming soon4
AMD Xilinx KCU105 Kintex UltraScale Development boardLPC✔️No1 1
AMD Xilinx VCU108 Virtex UltraScale Development boardHPC0✔️Coming soon4
AMD Xilinx VCU108 Virtex UltraScale Development boardHPC1✔️Coming soon4

Zynq Ultrascale+ boards

CarrierFMCCompatibleRef designSupported Ports
AMD Xilinx ZCU104 Zynq UltraScale+ Development boardLPC✔️✔️1 1
AMD Xilinx ZCU102 Zynq UltraScale+ Development boardHPC0✔️✔️4
AMD Xilinx ZCU102 Zynq UltraScale+ Development boardHPC1✔️✔️4
AMD Xilinx ZCU106 Zynq UltraScale+ Development boardHPC0✔️✔️4
AMD Xilinx ZCU106 Zynq UltraScale+ Development boardHPC1✔️No1
AMD Xilinx ZCU111 Zynq UltraScale+ Development boardFMC+✔️✔️4
AMD Xilinx ZCU208 Zynq UltraScale+ Development boardFMC+✔️✔️4
AMD Xilinx ZCU216 Zynq UltraScale+ Development boardFMC+✔️✔️4
Avnet UltraZed EV Carrier Zynq UltraScale+ Development boardHPC✔️✔️4
Trenz UltraITX+ Baseboard Zynq UltraScale+ Development boardHPC✔️Coming soon4

Ultrascale+ boards

CarrierFMCCompatibleRef designSupported Ports
AMD Xilinx VCU118 Virtex UltraScale+ Development boardHPC❌ Use FMC+ insteadNoNot supported
AMD Xilinx VCU118 Virtex UltraScale+ Development boardFMC+✔️Coming soon4

Versal boards

CarrierFMCCompatibleRef designSupported Ports
AMD Xilinx VCK190 Versal AI Core Development boardFMC+1✔️✔️4
AMD Xilinx VCK190 Versal AI Core Development boardFMC+2✔️✔️4
AMD Xilinx VEK280 Versal AI Edge Development boardFMC+✔️✔️4
AMD Xilinx VEK280 Versal HBM Development boardFMC+✔️✔️4
AMD Xilinx VMK180 Versal Prime Series Development boardFMC+1✔️✔️4
AMD Xilinx VMK180 Versal Prime Series Development boardFMC+2✔️✔️4
AMD Xilinx VPK120 Versal Premium Series Development boardFMC+✔️✔️4
AMD Xilinx VPK180 Versal Premium Series Development boardFMC+✔️✔️4

Compatibility requirements

If you need to determine the compatibility of a development board that is not listed here, or you are designing a carrier board to mate with the Ethernet FMC Max, please check your board against the list of requirements below.

VADJ

The development board must have the ability to supply a VADJ voltage between 1.2VDC and 2.5VDC. The Ethernet FMC Max has an EEPROM containing IPMI data to be used by a power management device. If the development board has such a power management device, an appropriate VADJ voltage will be applied automatically on power-up. Note that some development boards require the VADJ voltage to be configured by a DIP switch or jumper placement.

Gigabit transceivers

The FPGA or MPSoC device must have gigabit transceivers and they must be routed to the FMC connector. The PHYs of ports 0-3 are routed to transceivers DP0-DP3 respectively and these transceivers must be connected to the FPGA for the Ethernet ports to work.

Port labelSignal directionFMC PinFMC pin name
P0Link partner to FPGAC6/C7DP0_M2C_P/N
FPGA to Link partnerC2/C3DP0_C2M_P/N
P1Link partner to FPGAA2/A3DP1_M2C_P/N
FPGA to Link partnerA22/A23DP1_C2M_P/N
P2Link partner to FPGAA6/A7DP2_M2C_P/N
FPGA to Link partnerA26/A27DP2_C2M_P/N
P3Link partner to FPGAA10/A11DP3_M2C_P/N
FPGA to Link partnerA30/A31DP3_C2M_P/N

Note that low pin count (LPC) FMC connectors only have one possible GT connection (DP0). For this reason, carrier boards with LPC FMC connectors can only support a single Ethernet port (P0).

The GT clock reference (FMC pins GBTCLK0_M2C_P/N) should be connected to one of the GT reference clock inputs of the quad to which DP0-3 connect, or an adjacent quad.

The following FMC pins should ideally be connected to the FPGA as they provide extra functionality to the mezzanine card. These pins are not critical to the operation of the mezzanine card; it can operate without them if they are not connected on the carrier board.

FMC PinFMC nameNetDescription
G15LA12_PE0_RESET_N_TPort 0 PHY reset signal (active low)
G16LA12_NE1_RESET_N_TPort 1 PHY reset signal (active low)
H16LA11_PE2_RESET_N_TPort 2 PHY reset signal (active low)
H17LA11_NE3_RESET_N_TPort 3 PHY reset signal (active low)
G12LA08_PE0_GPIO0_TPort 0 PHY GPIO0 output
G13LA08_NE0_GPIO1_TPort 0 PHY GPIO1 output
H13LA07_PE1_GPIO0_TPort 1 PHY GPIO0 output
H14LA07_NE1_GPIO1_TPort 1 PHY GPIO1 output
G18LA16_PE2_GPIO0_TPort 2 PHY GPIO0 output
G19LA16_NE2_GPIO1_TPort 2 PHY GPIO1 output
H19LA15_PE3_GPIO0_TPort 3 PHY GPIO0 output
H20LA15_NE3_GPIO1_TPort 3 PHY GPIO1 output
D20LA17_CC_PMDCMDIO clock (shared bus)
D21LA17_CC_PMDIOMDIO data (shared bus)
D17LA13_PPG_1V0Power good output of 1.0V buck converter
D18LA13_NPG_2V5Power good output of 2.5V buck converter

  1. LPC connectors can only support 1-lane PCIe ↩︎ ↩︎ ↩︎ ↩︎ ↩︎

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