Pin Configuration

Pinout table

The Ethernet FMC has a low pin count FPGA Mezzanine Card (FMC) connector, providing the connections to the FPGA on the development board. The following table defines the pinout of the FMC connector and applies to both the Ethernet FMC and the Robust Ethernet FMC .

PinPin nameNetDescription
C1GNDGNDGround
C2DP0_C2M_PDP0_C2M_PNot used
C3DP0_C2M_NDP0_C2M_NNot used
C4GNDGNDGround
C5GNDGNDGround
C6DP0_M2C_PDP0_M2C_PNot used
C7DP0_M2C_NDP0_M2C_NNot used
C8GNDGNDGround
C9GNDGNDGround
C10LA06_PE1_RXD0Port 1 RGMII Receive Data Bit 0 (PHY-to-FPGA)
C11LA06_NE0_MDIOPort 0 MDIO Data (bidirectional)
C12GNDGNDGround
C13GNDGNDGround
C14LA10_PN/CNot used
C15LA10_NE1_RXD2Port 1 RGMII Receive Data Bit 2 (PHY-to-FPGA)
C16GNDGNDGround
C17GNDGNDGround
C18LA14_PREF_CLK_FSELReserved
C19LA14_NE1_MDIOPort 1 MDIO Data (bidirectional)
C20GNDGNDGround
C21GNDGNDGround
C22LA18_P_CCE3_RX_CLKPort 3 RGMII Receive Clock (PHY-to-FPGA)
C23LA18_N_CCE3_RX_CTRLPort 3 RGMII Receive Control (PHY-to-FPGA)
C24GNDGNDGround
C25GNDGNDGround
C26LA27_PE3_RXD1Port 3 RGMII Receive Data Bit 1 (PHY-to-FPGA)
C27LA27_NE3_RXD3Port 3 RGMII Receive Data Bit 3 (PHY-to-FPGA)
C28GNDGNDGround
C29GNDGNDGround
C30SCLI2C_SCLI2C Clock (FPGA-to-PHY)
C31SDAI2C_SDAI2C Data (bidirectional)
C32GNDGNDGround
C33GNDGNDGround
C34GA0GA0EEPROM Address Bit 1 (A1)
C3512P0V_112V012VDC (Not used)
C36GNDGNDGround
C3712P0V_212V012VDC (Not used)
C38GNDGNDGround
C393P3V_13V33.3VDC
C40GNDGNDGround
D1PG_C2MPGPower Good (Driven by carrier)
D2GNDGNDGround
D3GNDGNDGround
D4GBTCLK0_M2C_PN/CNot used
D5GBTCLK0_M2C_NN/CNot used
D6GNDGNDGround
D7GNDGNDGround
D8LA01_P_CCE1_RX_CLKPort 1 RGMII Receive Clock (PHY-to-FPGA)
D9LA01_N_CCE1_RX_CTRLPort 1 RGMII Receive Control (PHY-to-FPGA)
D10GNDGNDGround
D11LA05_PE0_MDCPort 0 MDIO Clock (FPGA-to-PHY)
D12LA05_NE0_RESET_NPort 0 PHY Reset (Active-Low)
D13GNDGNDGround
D14LA09_PE1_RXD1Port 1 RGMII Receive Data Bit 1 (PHY-to-FPGA)
D15LA09_NE1_RXD3Port 1 RGMII Receive Data Bit 3 (PHY-to-FPGA)
D16GNDGNDGround
D17LA13_PREF_CLK_OEEnable LVDS 125MHz Clock (Active-High, enabled by default with pull-up)
D18LA13_NE1_MDCPort 1 MDIO Clock (FPGA-to-PHY)
D19GNDGNDGround
D20LA17_P_CCE2_RX_CLKPort 2 RGMII Receive Clock (PHY-to-FPGA)
D21LA17_N_CCN/CNot used
D22GNDGNDGround
D23LA23_PE2_RXD2Port 2 RGMII Receive Data Bit 2 (PHY-to-FPGA)
D24LA23_NE2_RXD3Port 2 RGMII Receive Data Bit 3 (PHY-to-FPGA)
D25GNDGNDGround
D26LA26_PE3_RXD0Port 3 RGMII Receive Data Bit 0 (PHY-to-FPGA)
D27LA26_NE3_RXD2Port 3 RGMII Receive Data Bit 2 (PHY-to-FPGA)
D28GNDGNDGround
D29TCKN/CNot used
D30TDITDI-TDOJTAG TDI (Connects to TDO to close JTAG chain)
D31TDOTDI-TDOJTAG TDO (Connects to TDI to close JTAG chain)
D323P3VAUXN/CNot used
D33TMSN/CNot used
D34TRST_LN/CNot used
D35GA1GA1EEPROM Address Bit 0 (A0)
D363P3V_23V33.3VDC
D37GNDGNDGround
D383P3V_33V33.3VDC
D39GNDGNDGround
D403P3V_43V33.3VDC
G1GNDGNDGround
G2CLK1_M2C_PN/CNot used
G3CLK1_M2C_NN/CNot used
G4GNDGNDGround
G5GNDGNDGround
G6LA00_P_CCE0_RX_CLKPort 0 RGMII Receive Clock (PHY-to-FPGA)
G7LA00_N_CCE0_RX_CTRLPort 0 RGMII Receive Control (PHY-to-FPGA)
G8GNDGNDGround
G9LA03_PE0_RXD2Port 0 RGMII Receive Data Bit 2 (PHY-to-FPGA)
G10LA03_NE0_RXD3Port 0 RGMII Receive Data Bit 3 (PHY-to-FPGA)
G11GNDGNDGround
G12LA08_PE0_TXD1Port 0 RGMII Transmit Data Bit 1 (FPGA-to-PHY)
G13LA08_NE0_TXD2Port 0 RGMII Transmit Data Bit 2 (FPGA-to-PHY)
G14GNDGNDGround
G15LA12_PN/CNot used
G16LA12_NE1_TXD0Port 1 RGMII Transmit Data Bit 0 (FPGA-to-PHY)
G17GNDGNDGround
G18LA16_PE1_TXD2Port 1 RGMII Transmit Data Bit 2 (FPGA-to-PHY)
G19LA16_NE1_TXD3Port 1 RGMII Transmit Data Bit 3 (FPGA-to-PHY)
G20GNDGNDGround
G21LA20_PE2_RX_CTRLPort 2 RGMII Receive Control (PHY-to-FPGA)
G22LA20_NE2_RXD0Port 2 RGMII Receive Data Bit 0 (PHY-to-FPGA)
G23GNDGNDGround
G24LA22_PE2_TXD1Port 2 RGMII Transmit Data Bit 1 (FPGA-to-PHY)
G25LA22_NE2_TXD2Port 2 RGMII Transmit Data Bit 2 (FPGA-to-PHY)
G26GNDGNDGround
G27LA25_PE2_TX_CTRLPort 2 RGMII Transmit Control (FPGA-to-PHY)
G28LA25_NE2_MDIOPort 2 MDIO Data (bidirectional)
G29GNDGNDGround
G30LA29_PN/CNot used
G31LA29_NE3_TXD0Port 3 RGMII Transmit Data Bit 0 (FPGA-to-PHY)
G32GNDGNDGround
G33LA31_PE3_TXD2Port 3 RGMII Transmit Data Bit 2 (FPGA-to-PHY)
G34LA31_NE3_TXD3Port 3 RGMII Transmit Data Bit 3 (FPGA-to-PHY)
G35GNDGNDGround
G36LA33_PN/CNot used
G37LA33_NN/CNot used
G38GNDGNDGround
G39VADJ_3VADJI/O Supply Voltage (1.8VDC or 2.5VDC)
G40GNDGNDGround
H1VREF_A_M2CN/CNot used
H2PRSNT_M2C_LGNDGround
H3GNDGNDGround
H4CLK0_M2C_PREF_CLK_PLVDS 125MHz Precision Clock to FPGA
H5CLK0_M2C_NREF_CLK_NLVDS 125MHz Precision Clock to FPGA
H6GNDGNDGround
H7LA02_PE0_RXD0Port 0 RGMII Receive Data Bit 0 (PHY-to-FPGA)
H8LA02_NE0_RXD1Port 0 RGMII Receive Data Bit 1 (PHY-to-FPGA)
H9GNDGNDGround
H10LA04_PE0_TXD0Port 0 RGMII Transmit Data Bit 0 (FPGA-to-PHY)
H11LA04_NE0_TX_CLKPort 0 RGMII Transmit Clock (FPGA-to-PHY)
H12GNDGNDGround
H13LA07_PE0_TXD3Port 0 RGMII Transmit Data Bit 3 (FPGA-to-PHY)
H14LA07_NE0_TX_CTRLPort 0 RGMII Transmit Control (FPGA-to-PHY)
H15GNDGNDGround
H16LA11_PE1_TXD1Port 1 RGMII Transmit Data Bit 1 (FPGA-to-PHY)
H17LA11_NE1_TX_CLKPort 1 RGMII Transmit Clock (FPGA-to-PHY)
H18GNDGNDGround
H19LA15_PE1_TX_CTRLPort 1 RGMII Transmit Control (FPGA-to-PHY)
H20LA15_NE1_RESET_NPort 1 PHY Reset (Active-Low)
H21GNDGNDGround
H22LA19_PE2_RXD1Port 2 RGMII Receive Data Bit 1 (PHY-to-FPGA)
H23LA19_NE2_TXD0Port 2 RGMII Transmit Data Bit 0 (FPGA-to-PHY)
H24GNDGNDGround
H25LA21_PE2_TX_CLKPort 2 RGMII Transmit Clock (FPGA-to-PHY)
H26LA21_NE2_TXD3Port 2 RGMII Transmit Data Bit 3 (FPGA-to-PHY)
H27GNDGNDGround
H28LA24_PE2_MDCPort 2 MDIO Clock (FPGA-to-PHY)
H29LA24_NE2_RESET_NPort 2 PHY Reset (Active-Low)
H30GNDGNDGround
H31LA28_PE3_TXD1Port 3 RGMII Transmit Data Bit 1 (FPGA-to-PHY)
H32LA28_NE3_TX_CLKPort 3 RGMII Transmit Clock (FPGA-to-PHY)
H33GNDGNDGround
H34LA30_PE3_TX_CTRLPort 3 RGMII Transmit Control (FPGA-to-PHY)
H35LA30_NE3_MDCPort 3 MDIO Clock (FPGA-to-PHY)
H36GNDGNDGround
H37LA32_PE3_MDIOPort 3 MDIO Data (bidirectional)
H38LA32_NE3_RESET_NPort 3 PHY Reset (Active-Low)
H39GNDGNDGround
H40VADJ_4VADJI/O Supply Voltage (1.8VDC or 2.5VDC)

Net lengths

The table below lists the trace lengths.

NetLength (mils)
Port 0E0_TXD0935.369
E0_TXD11022.274
E0_TXD21016.451
E0_TXD3973.815
E0_TX_CLK926.463
E0_TX_CTRL1025.089
E0_RXD0987.273
E0_RXD11034.127
E0_RXD21066.126
E0_RXD3989.16
E0_RX_CLK1055.744
E0_RX_CTRL1018.718
Port 1E1_TXD0821.649
E1_TXD1781.117
E1_TXD2830.455
E1_TXD3867.309
E1_TX_CLK767.898
E1_TX_CTRL847.395
E1_RXD01336.123
E1_RXD11345.882
E1_RXD21336.42
E1_RXD31296.088
E1_RX_CLK1262.112
E1_RX_CTRL1277.099
Port 2E2_TXD0910.149
E2_TXD1902.087
E2_TXD2922.798
E2_TXD3882.68
E2_TX_CLK895.55
E2_TX_CTRL968.80
E2_RXD01106.905
E2_RXD11133.374
E2_RXD21165.735
E2_RXD31169.388
E2_RX_CLK1105.029
E2_RX_CTRL1143.103
Port 3E3_TXD01046.468
E3_TXD1983.755
E3_TXD21062.666
E3_TXD31075.708
E3_TX_CLK995.204
E3_TX_CTRL1056.065
E3_RXD01535.853
E3_RXD11502.359
E3_RXD21499.971
E3_RXD31590.42
E3_RX_CLK1512.856
E3_RX_CTRL1545.37
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