Board Revision History

Rev 1-1

  • Date of first manufacture: 2014-12-15
  • First board release
  • Supports VADJ 2.5V only

Rev B

  • Date of first manufacture: 2015-03-27
  • Increased via tenting diameters underneath QFNs to increase manufacturing yield
  • Optimizations to bottom layer planes
  • Added solder jumpers to REF_CLK_FSEL 1 and REF_CLK_OE 2 signals (see note 3).
  • 125MHz oscillator VCC now connected to 3.3VDC

Rev C

  • Date of first manufacture: 2015-05-07
  • Increased via tenting diameters underneath QFNs to increase manufacturing yield
  • Removed “2V5” from silkscreen

Rev D

  • Date of first manufacture: 2015-07-16
  • R24, R25 changed to 240R 0402 to reduce part count
  • Via tenting under QFNs replaced by via-in-pad

Rev E

  • Date of first manufacture: 2016-05-02
  • Changed 125MHz oscillator to Micrel MEMS part DSC1123CI2-125.0000 to replace obsolete On Semi part NBXDPA019LNHTAG
  • Removed FSEL option - consequence of the oscillator part change
  • Added buffer to CLK_EN input to allow it to be driven at 1.8V
  • Removed the solder jumpers for FSEL and CLK_EN
  • Expanded FMC solder paste pads to improve manufacturing yield
  • Changed chassis filter capacitor to 1kV in 0805 package

Rev F

  • Date of first manufacture: 2020-02-04
  • JG0-0025NL Quad RJ45 footprint optimized to facilitate assembly
  • Added CE logo to silkscreen

  1. REF_CLK_FSEL is an input of the clock oscillator and allows the output frequency to be set to either 125MHz or 250MHz. Floating this pin results in an output of 125MHz. ↩︎

  2. REF_CLK_OE is the output enable input of the clock oscillator. Floating this pin results in output being enabled. ↩︎

  3. These REF_CLK_FSEL and REF_CLK_OE jumpers are shorted on the 2.5V version to allow the signals to be driven by the carrier board. These jumpers are left OPEN on the 1.8V version, as 1.8VDC is not sufficient to drive them. This effectively floats the inputs and results in an always-enabled output of 125MHz. ↩︎