Compatible Boards

This section of the documentation aims to list all of the development boards for which compatibility with the Quad SFP28 FMC has been checked, and to list constraints and any notes concerning special requirements or limitations with the board.

List of boards #

The following development boards have been verified compatible with the Quad SFP28 FMC. For more detailed information regarding compatibility with a particular development board, including the availability of an example design, click on the name of the board in the table below.

Note that we are still working on the reference designs for these boards and we expect them to be available by September 2024.

Series-7 boards #

UltraScale boards #

Zynq Ultrascale+ boards #

Ultrascale+ boards #

Versal boards #

Compatibility requirements #

If you need to determine the compatibility of a development board that is not listed here, or you are designing a carrier board to mate with the Quad SFP28 FMC, please check your board against the list of requirements below.

VADJ #

The development board must have the ability to supply a VADJ voltage between 1.2VDC and 3.3VDC. The Quad SFP28 FMC has an EEPROM containing IPMI data to be used by a power management device. If the development board has such a power management device, an appropriate VADJ voltage will be applied automatically on power-up. Note that some development boards require the VADJ voltage to be configured by a DIP switch or jumper placement.

Gigabit transceivers #

The FPGA or MPSoC device must have gigabit transceivers and they must be routed to the FMC connector. The SFP28 slots 0-3 are routed to transceivers DP0-DP3 respectively and these transceivers must be connected to the FPGA for the SFP28 slots to work.

Note that low pin count (LPC) FMC connectors only have one possible GT connection (DP0). For this reason, carrier boards with LPC FMC connectors can only support a single SFP28 slot (slot 0).

At least one of the GT clock references (FMC pins GBTCLK0_M2C_P/N and GBTCLK1_M2C_P/N) should be connected to one of the GT reference clock inputs of the quad to which DP0-3 connect, or an adjacent quad.

Required I/O #

The following FMC pins must be connected to the FPGA as they provide critical I/O to the mezzanine card.

Featured I/O #

The following FMC pins should ideally be connected to the FPGA as they provide extra functionality to the mezzanine card. These pins are not critical to the operation of the mezzanine card; it can operate without them if they are not connected on the carrier board.