Example Designs
The example designs for the Quad SFP28 FMC are hosted on Github.
| Example Designs | |||
|---|---|---|---|
| 10G/25G Ethernet Subsystem Example Design | More info | Git repo | Docs |
Note that all of our example designs were developed using Xilinx software tools and
either the
AMD Xilinx AXI 1G/2.5G Ethernet Subsystem IP
or the
AMD Xilinx 10G/25G Ethernet Subsystem IP
IP. If you wish to use these
example designs, you must at least have an evaluation license for the Ethernet IP that is used in
the design. See instructions on obtaining a license here.
10G/25G Ethernet Subsystem based example
Description
This example design is based on Xilinx’s soft MAC (ie. FPGA implemented), the AMD Xilinx 10G/25G Ethernet Subsystem IP , that can be found in the Vivado IP Catalog. As the MAC is implemented in the FPGA fabric, this example is ideal for pure FPGA designs or Zynq/ZynqMP designs that require some packet processing to be performed in the FPGA.
Links
PS GEM based example
Description
This example design utilizes the Gigabit Ethernet MACs (GEMs) that are embedded into the Processing System (PS) of the Zynq 7000™ and Zynq Ultrascale+™ devices. The embedded MACs used in this example design do not use up any of the FPGA fabric, which makes it ideal for applications that need to use the FPGA for other purposes.
Links
- Coming soon