Programming Guide

This section provides the details of the programming requirements to operate the Ethernet FMC hardware and customise functionality.


Some of the SFP I/Os must be driven by the FPGA to fixed levels in order to configure the SFP/SPF+/SFP28 modules for normal operation.

Optical output

SFP module input TX_DISABLE allows the FPGA to disable the optical output if so desired. In normal operation however, this input should be driven LOW to enable optical output.

NetDescriptionFMC pinValue for normal operation
SFP0_TX_DISABLE_TSlot 0: Disables optical outputLA03_PLOW (0)
SFP1_TX_DISABLE_TSlot 1: Disables optical outputLA12_PLOW (0)
SFP2_TX_DISABLE_TSlot 2: Disables optical outputLA15_NLOW (0)
SFP3_TX_DISABLE_TSlot 3: Disables optical outputLA17_CC_NLOW (0)

Rate select

The SFP module inputs, RS0 and RS1, generally allow the FPGA to configure the module for different link speeds or performance levels. However, their specific function may vary by vendor. Please refer to the datasheet of your SFP/SFP+/SFP28 module for detailed information on configuring these pins. Note that some modules do not use these pins at all.

If you are unsure what levels to apply to RS0 and RS1, or if your modules do not require them, we recommend driving the signals to the constant values shown in the table below.

NetDescriptionFMC pinValue
SFP0_RS1_TSlot 0: Rate select 1LA02_PLOW (0)
SFP0_RS0_TSlot 0: Rate select 0LA02_NLOW (0)
SFP1_RS1_TSlot 1: Rate select 1LA08_PLOW (0)
SFP1_RS0_TSlot 1: Rate select 0LA08_NLOW (0)
SFP2_RS1_TSlot 2: Rate select 1LA10_PLOW (0)
SFP2_RS0_TSlot 2: Rate select 0LA10_NLOW (0)
SFP3_RS1_TSlot 3: Rate select 1LA14_PLOW (0)
SFP3_RS0_TSlot 3: Rate select 0LA14_NLOW (0)

I2C Switch

The I2C switch ( PCA9548 ) is connected to the PS I2C bus and allows the FPGA to communicate with the SFP/SFP+/SFP28 modules and the jitter-attenuating clock multiplier. The I2C switch has address 0x70.


The PS I2C bus signals are connected to the FMC pins listed in the table below:

Net NameDescriptionFMC pin
PL_I2C_SCL_TI2C clock (SCL)LA11_P
PL_I2C_SDA_TI2C data (SDA)LA11_N

The channels of the I2C switch are connected as shown in the table below:

I2C DeviceSwitch channelDevice I2C address
SFP28 Slot 00Module dependent
SFP28 Slot 11Module dependent
SFP28 Slot 22Module dependent
SFP28 Slot 33Module dependent
Clock multiplier40x68

Note that the I2C addresses of the SFP/SFP+/SFP28 modules are dependent on the specific module used. Refer to the module datasheet for this information.

Clock multiplier

The jitter-attenuating clock multiplier ( Skyworks, Si5328 ) must be configured via the PS I2C bus to enable appropriate clocks for the SFP/SFP+/SFP28 modules used. The Si5328 has the I2C address 0x68.


Refer to the Si5328 datasheet for detailed information on the device registers and how to configure the clock outputs.


The 2K EEPROM is intended to store information that identifies the mezzanine card and also specifies the power supplies required by the card. This information is typically read by the system power management on the carrier board when it is powered up. In typical user applications, it should not be necessary to read the data on the EEPROM, and we highly recommend against writing to the EEPROM. Nevertheless, if you wish to access the EEPROM, it can be read and written to at the I2C address 0x50.


The EEPROM sits on the FMC card’s dedicated I2C bus. The FMC pins of the EEPROM’s I2C bus are shown below, and it is up to the user to determine their corresponding connections to the FPGA/MPSoC on the carrier board being used.

I2C bus signalFMC pin nameFMC pin number
SCL (clock)SCLC30
SDA (data)SDAC31


The Opsero FMC EEPROM Tool can be used to verify, reprogram or update the EEPROM contents of Opsero FMC products using an FPGA or MPSoC board such as the ZCU102 or VCU118 board.

Supported boards

The tool currently supports the following FPGA/MPSoC boards. You must have at least one of these boards in order to use the tool.


The tool can be downloaded at the link below:

Opsero FMC EEPROM Tool v1.5

The zip file contains a boot file (bitstream or BOOT.bin) for each of the supported boards.

Usage instructions

To run the tool, follow these steps:

  1. Plug the FMC card you wish to reprogram into one of the FMC connectors of your FPGA/MPSoC board. The tool is designed to probe all of the FMC connectors on the FPGA/MPSoC board.

  2. If you are using the ZedBoard, be sure to set the VADJ jumper setting to 1.8V. If you are using the KC705, be sure that your FMC card can support a VADJ of 2.5V, which is the default setting of that board.

  3. Connect the UART of your FPGA/MPSoC board to a PC.

  4. For Zynq and Zynq MP boards, a BOOT.bin file is provided. Copy this file to your board’s SD card and configure it to boot from SD card. Then plug the SD card back into the board and power it up.

  5. For FPGA boards, a bitstream is provided with an embedded ELF file. Power up your FPGA/MPSoC board and then download the bitstream to the FPGA board using the Vivado Hardware Manager tool.

  6. Open a terminal program such as Putty and connect to the serial port of your FPGA/MPSoC board. If you see nothing in the terminal window, press ENTER to redisplay the menu.

  7. Use the menu options to do the following:

    • Program the EEPROM (p)
      You will be asked to select the FMC product from a list, and also to enter the product’s serial number. Note that entering incorrect information here can lead to your FMC card being damaged by a VADJ voltage that is greater than it’s true rating. If you are not sure about the product to select here, please contact Opsero first.