Compatible Boards

This section of the documentation aims to list all of the development boards for which compatibility with the Ethernet FMC has been checked, and to list constraints and any notes concerning special requirements or limitations with the board.

List of boards

The following development boards have been verified compatible with the Ethernet FMC. For more detailed information regarding compatibility with a particular development board, including the availability of an example design, click on the name of the board in the table below.

Zynq-7000 boards

Development boardCompatible withCompatible P/Ns
ZedBoardEthernet FMC 2.5VOP031-2V5
Robust Ethernet FMC 2.5VOP041-2V5
ZC702Ethernet FMC 2.5VOP031-2V5
Robust Ethernet FMC 2.5VOP041-2V5
ZC706Ethernet FMC 2.5VOP031-2V5
Robust Ethernet FMC 2.5VOP041-2V5
PicoZed FMC Carrier v2Robust Ethernet FMC 1.8VOP041-1V8
Robust Ethernet FMC 2.5VOP041-2V5
MicroZed FMC CarrierRobust Ethernet FMC 2.5VOP041-2V5

Zynq Ultrascale+ boards

Development boardCompatible withCompatible P/Ns
ZCU102 Rev-DEthernet FMC 1.8VOP031-1V8
Robust Ethernet FMC 1.8VOP041-1V8
ZCU102Ethernet FMC 1.8VOP031-1V8
Robust Ethernet FMC 1.8VOP041-1V8
ZCU104Ethernet FMC 1.8VOP031-1V8
Robust Ethernet FMC 1.8VOP041-1V8
ZCU106Ethernet FMC 1.8VOP031-1V8
Robust Ethernet FMC 1.8VOP041-1V8
UltraZed EGRobust Ethernet FMC 1.8VOP041-1V8
UltraZed EVEthernet FMC 1.8VOP031-1V8
Robust Ethernet FMC 1.8VOP041-1V8
TEBF0808Robust Ethernet FMC 1.8VOP041-1V8
Mercury PE1 400Ethernet FMC 1.8VOP031-1V8
Robust Ethernet FMC 1.8VOP041-1V8

Zynq UltraScale+ RFSoC boards

Development boardCompatible withCompatible P/Ns
ZCU111Ethernet FMC 1.8VOP031-1V8
Robust Ethernet FMC 1.8VOP041-1V8
ZCU208Ethernet FMC 1.8VOP031-1V8
Robust Ethernet FMC 1.8VOP041-1V8

Series-7 boards

Development boardCompatible withCompatible P/Ns
AC701Ethernet FMC 2.5VOP031-2V5
Robust Ethernet FMC 2.5VOP041-2V5
KC705Ethernet FMC 2.5VOP031-2V5
Robust Ethernet FMC 2.5VOP041-2V5
VC707Ethernet FMC 1.8VOP031-1V8
Robust Ethernet FMC 1.8VOP041-1V8
VC709Ethernet FMC 1.8VOP031-1V8
Robust Ethernet FMC 1.8VOP041-1V8

Ultrascale and Ultrascale+ boards

Development boardCompatible withCompatible P/Ns
KCU105Ethernet FMC 1.8VOP031-1V8
Robust Ethernet FMC 1.8VOP041-1V8
VCU108Ethernet FMC 1.8VOP031-1V8
Robust Ethernet FMC 1.8VOP041-1V8
VCU118Ethernet FMC 1.8VOP031-1V8
Robust Ethernet FMC 1.8VOP041-1V8
HTG-840Ethernet FMC 1.8VOP031-1V8
Robust Ethernet FMC 1.8VOP041-1V8

Other boards

Development boardCompatible withCompatible P/Ns
Arria 10 AttilaRobust Ethernet FMC 1.8VOP041-1V8

Compatibility requirements

If you need to determine the compatibility of a development board that is not listed here, or you are designing a carrier board to mate with the Ethernet FMC, please check your board against the list of requirements below.

VADJ

The development board must have the ability to supply a VADJ voltage of either 1.8VDC or 2.5VDC. The Ethernet FMC has an EEPROM containing IPMI data to be used by a power management device. If the development board has such a power management device, the correct VADJ will be applied automatically on power-up. Note that some development boards require the VADJ voltage to be configured by a DIP switch or jumper placement.

Port 0

  • FMC pins LA00, LA02, LA03, LA04, LA05, LA06, LA07, LA08 must be connected to the FPGA
  • All of the above pins must be connected to the same I/O bank
  • Ideally, LA00 should be routed to a clock capable pin

Port 1

  • FMC pins LA01, LA06, LA09, LA10, LA11, LA12, LA13, LA14, LA15, LA16 must be connected to the FPGA
  • All of the above pins must be connected to the same I/O bank
  • Ideally, LA01 should be routed to a clock capable pin

Port 2

  • FMC pins LA17, LA19, LA20, LA21, LA22, LA23, LA24, LA25 must be connected to the FPGA
  • All of the above pins must be connected to the same I/O bank
  • Ideally, LA17 should be routed to a clock capable pin

Port 3

  • FMC pins LA18, LA26, LA27, LA28, LA29, LA30, LA31, LA32 must be connected to the FPGA
  • All of the above pins must be connected to the same I/O bank
  • Ideally, LA18 should be routed to a clock capable pin

If any of LA00, LA01, LA17 or LA18 are not connected to a clock capable pin, you may experience difficulty achieving timing closure in your FPGA design. In some cases, timing closure can be still be achieved using non-clock capable pins by using carefully designed timing constraints.

Limitations when using HR (high-range) I/Os

Some FMC carriers such as the ZedBoard, AC701, KC705, ZC702 and ZC706 have FMC connectors that route to HR (high-range) I/Os. Although HR I/Os can be operated from 1.2V to 3.3V, when it comes to LVDS they are actually limited to the I/O standard LVDS_25 (according to UG471). For this reason, we recommend using the 2.5V version Ethernet FMC or Robust Ethernet FMC on these carriers. If you are using the 2.5V version Ethernet FMC or Robust Ethernet FMC on these carriers, then you do not need to implement the work-arounds described in this section.

Using Ethernet FMC 1.8V with HR I/Os

The Ethernet FMC has a 125MHz clock which is routed to the FMC connector as an LVDS signal in compliance with the VITA 57.1 standard. On the aforementioned carriers, this signal is received by the FPGA on a HR bank and therefore must be defined in your Vivado design as LVDS_25. This would normally imply that your I/O banks should be powered at 2.5V, which would conflict with the 1.8V requirement of the Ethernet FMC.

If you must use the 1.8V version Ethernet FMC or Robust Ethernet FMC on a carrier with an FMC connector that connects to HR I/Os, then you have two options to get around the limitation:

Option 1: Use an alternative clock source

If you can supply the 125MHz MAC clock from another source, such as a precision clock oscillator on the FPGA development board, then you do not need to define the Ethernet FMC’s LVDS clock in your HDL design. This is the ideal solution, but is not always possible.

Option 2: Use the work-around

To get around this limitation, Xilinx proposes a work-around in answer record 43989. To implement the work-around, you need to be able to make a hardware modification to your carrier board.

  1. Add a 100 ohm external termination resistor to the FPGA input pins that receive the 125MHz LVDS clock signal.

  1. Use 2.5V I/O standards in the Vivado design:

    • Define the clock in your Vivado design using the IOSTANDARD: LVDS_25.
    • Define the other FMC I/Os using the IOSTANDARD: LVCMOS_25 (we are required to use 2.5V standards on the entire bank).
  2. Configure your carrier to power VADJ at 1.8V.

In other words, your Vivado design must be configured for VADJ of 2.5V but you will actually power VADJ at 1.8V. This is a valid work-around which is described by answer record 43989, with the condition that an external termination resistor must be installed. The reason that you need an external termination resistor is that the circuit for producing the internal termination resistor expects a power supply that corresponds to the IOSTANDARDs defined in the Vivado design. According to answer record 43989, it is prohibited to enable the internal differential termination resistor (DIFF_TERM=TRUE) if you configure your design for one supply voltage and power the I/O banks at another.

Walk me through the answer record

Configuring an I/O bank at one voltage and supplying it with a different voltage is a workaround proposed by Xilinx answer record 43989.

Following the flow chart in the answer record for these conditions:

  • LVDS_25 HR bank
  • Input (we only need the clock inputs to be LVDS)
  • VCCO != 2.5V

We get a VIN requirement of:

TxVOCM + TxVOD/2 < VCCO + 0.2V

Now, according to the datasheet of the clock oscillator:

Vod (magnitude of the differential voltage) = 450mV (worst case)
Vocm (common mode voltage) = (1600 + 900)/2 = 1250mV (worst case)

By plugging these values into the above condition, using VCCO = 1.8, we can confirm that the VIN requirement is indeed satisfied.

Board notes

ZedBoard

Example Designs
AXI Ethernet Example DesignMore infoGit repoDocs
PS GEM Example DesignMore infoGit repoDocs
Maximum Throughput Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 2.5V2.5VOP031-2V5
Robust Ethernet FMC 2.5V2.5VOP041-2V5

See note 1 for more information regarding the VADJ options.

Connectors

  • LPC: Satisfies all of the Ethernet FMC requirements.

Setting VADJ

The VADJ setting on this development board is determined by a pin header labelled J18. It should be set to 1.8V or 2.5V depending on the voltage specification of the Ethernet FMC being used.

AC701

Example Designs
AXI Ethernet Example DesignMore infoGit repoDocs
Processorless Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 2.5V2.5VOP031-2V5
Robust Ethernet FMC 2.5V2.5VOP041-2V5

See note 1 for more information regarding the VADJ options.

Connectors

  • HPC: Satisfies all of the Ethernet FMC requirements.

KC705

Example Designs
AXI Ethernet Example DesignMore infoGit repoDocs
Maximum Throughput Example DesignMore infoGit repoDocs
Processorless Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 2.5V2.5VOP031-2V5
Robust Ethernet FMC 2.5V2.5VOP041-2V5

See note 1 for more information regarding the VADJ options.

Connectors

  • LPC: Satisfies all of the Ethernet FMC requirements.
  • HPC: Satisfies all of the Ethernet FMC requirements.

VC707

Example Designs
AXI Ethernet Example DesignMore infoGit repoDocs
Processorless Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 1.8V1.8VOP031-1V8
Robust Ethernet FMC 1.8V1.8VOP041-1V8

See note 2 for more information regarding the VADJ options.

Connectors

  • HPC1: Satisfies all of the Ethernet FMC requirements.
  • HPC2: Satisfies all of the Ethernet FMC requirements.

VC709

Example Designs
AXI Ethernet Example DesignMore infoGit repoDocs
Processorless Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 1.8V1.8VOP031-1V8
Robust Ethernet FMC 1.8V1.8VOP041-1V8

See note 2 for more information regarding the VADJ options.

Connectors

  • HPC: Satisfies all of the Ethernet FMC requirements.

ZC702

Example Designs
AXI Ethernet Example DesignMore infoGit repoDocs
PS GEM Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 2.5V2.5VOP031-2V5
Robust Ethernet FMC 2.5V2.5VOP041-2V5

See note 1 for more information regarding the VADJ options.

Connectors

  • LPC1: Satisfies all of the Ethernet FMC requirements.
  • LPC2: Satisfies all of the Ethernet FMC requirements.

ZC706

Example Designs
AXI Ethernet Example DesignMore infoGit repoDocs
PS GEM Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 2.5V2.5VOP031-2V5
Robust Ethernet FMC 2.5V2.5VOP041-2V5

See note 1 for more information regarding the VADJ options.

Connectors

  • LPC: Satisfies all of the Ethernet FMC requirements.
  • HPC: Pins LA18_CC and LA17_CC of the HPC connector are routed to non-clock-capable pins so they cannot properly receive the RGMII receive clocks for ports 2 and 3 of the Ethernet FMC. However this connector satisfies all of the requirements for ports 0 and 1 (note however that there is no example design for this connector at this time).

PicoZed FMC Carrier Card V2

Note that the choice of VADJ depends on the SoM being used on this carrier.

Example Designs
AXI Ethernet Example DesignMore infoGit repoDocs
PS GEM Example DesignMore infoGit repoDocs
Maximum Throughput Example DesignMore infoGit repoDocs

When using the PicoZed SoM 7015 or 7020

Mates withVADJBuy
Robust Ethernet FMC 2.5V2.5VOP041-2V5
See note 1 for more information regarding the VADJ options.

When using the PicoZed SoM 7030

Mates withVADJBuy
Robust Ethernet FMC 1.8V1.8VOP041-1V8

Connectors

  • LPC: Satisfies all of the Ethernet FMC requirements.

MicroZed FMC Carrier

Example Designs
AXI Ethernet Example DesignMore infoGit repoDocs
PS GEM Example DesignMore infoGit repoDocs
Maximum Throughput Example DesignMore infoGit repoDocs
Mates withVADJBuy
Robust Ethernet FMC 2.5V2.5VOP041-2V5

See note 1 for more information regarding the VADJ options.

Connectors

  • LPC: Satisfies all of the Ethernet FMC requirements.

Mini-ITX 7100 Base Kit

The Mini-ITX cannot be used with any version of the Ethernet FMC. The FMC connector on this carrier was positioned such that the FMC card would face inwards, with the I/O connectors (in this case the RJ45 connectors) pointing towards the center of the board. In the case of the Ethernet FMC, the Zynq-7000 device and heat-sink would block access to the RJ45 connectors, making them unusable.

UltraZed EG PCIe Carrier Card

Example Designs
PS GEM Example DesignMore infoGit repoDocs
Mates withVADJBuy
Robust Ethernet FMC 1.8V1.8VOP041-1V8

See note 2 for more information regarding the VADJ options.

Connectors

  • LPC: Satisfies all of the Ethernet FMC requirements.

UltraZed EV Carrier Card

Example Designs
AXI Ethernet Example DesignMore infoGit repoDocs
PS GEM Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 1.8V1.8VOP031-1V8
Robust Ethernet FMC 1.8V1.8VOP041-1V8

Connectors

  • HPC: Satisfies all of the Ethernet FMC requirements.

VADJ

This board has a fixed 1.8V VADJ voltage.

ML605

Mates withVADJBuy
Ethernet FMC 2.5V2.5VOP031-2V5
Robust Ethernet FMC 2.5V2.5VOP041-2V5

See note 3 for more information regarding the VADJ options.

Example designs

No example designs are currently available for this development board.

Connectors

  • LPC: Satisfies all of the Ethernet FMC requirements.
  • HPC: Satisfies all of the Ethernet FMC requirements.

KCU105

Example Designs
AXI Ethernet Example DesignMore infoGit repoDocs
Processorless Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 1.8V1.8VOP031-1V8
Robust Ethernet FMC 1.8V1.8VOP041-1V8

See note 2 for more information regarding the VADJ options.

Connectors

  • LPC: Satisfies all of the Ethernet FMC requirements.
  • HPC: Satisfies all of the Ethernet FMC requirements.

ZCU102 Rev-D

Example Designs
AXI Ethernet Example DesignMore infoGit repoDocs
PS GEM Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 1.8V1.8VOP031-1V8
Robust Ethernet FMC 1.8V1.8VOP041-1V8

See note 2 for more information regarding the VADJ options.

Connectors

  • HPC0: Satisfies all of the Ethernet FMC requirements.
  • HPC1: The I/O pins for port 2 are routed to separate I/O banks by this connector, making it unusable. The other ports however may be used.

ZCU102

Example Designs
AXI Ethernet Example DesignMore infoGit repoDocs
PS GEM Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 1.8V1.8VOP031-1V8
Robust Ethernet FMC 1.8V1.8VOP041-1V8

See note 2 for more information regarding the VADJ options.

Connectors

  • HPC0: Satisfies all of the Ethernet FMC requirements.
  • HPC1: The I/O pins for port 2 are routed to separate I/O banks by this connector, making it unusable. The other ports however may be used.

ZCU104

Example Designs
PS GEM Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 1.8V1.8VOP031-1V8
Robust Ethernet FMC 1.8V1.8VOP041-1V8

See note 2 for more information regarding the VADJ options.

Connectors

  • LPC: Satisfies all of the Ethernet FMC requirements.

ZCU106

Example Designs
PS GEM Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 1.8V1.8VOP031-1V8
Robust Ethernet FMC 1.8V1.8VOP041-1V8

See note 2 for more information regarding the VADJ options.

Connectors

  • HPC0: Satisfies all of the Ethernet FMC requirements.
  • HPC1: This connector only has LA00-LA16 pins connected to the FPGA, therefore it can only support ports 0 and 1.

ZCU111

Example Designs
PS GEM Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 1.8V1.8VOP031-1V8
Robust Ethernet FMC 1.8V1.8VOP041-1V8

See note 2 for more information regarding the VADJ options.

Connectors

  • FMC+: Satisfies all of the Ethernet FMC requirements.

ZCU208

Mates withVADJBuy
Ethernet FMC 1.8V1.8VOP031-1V8
Robust Ethernet FMC 1.8V1.8VOP041-1V8

See note 2 for more information regarding the VADJ options.

Example designs

No example designs are currently available for this development board.

Connectors

  • FMC+: Satisfies all of the Ethernet FMC requirements.

VCU108

Example Designs
AXI Ethernet Example DesignMore infoGit repoDocs
Processorless Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 1.8V1.8VOP031-1V8
Robust Ethernet FMC 1.8V1.8VOP041-1V8

See note 2 for more information regarding the VADJ options.

Connectors

  • HPC0: Satisfies all of the Ethernet FMC requirements.
  • HPC1: Satisfies all of the Ethernet FMC requirements.

VCU110

The Xilinx VCU110 cannot be used with any Ethernet FMC. The VCU110 board’s FMC connectors are only partially routed to the FPGA. Many I/Os that are required by the Ethernet FMC are not connected on this board.

VCU118

Example Designs
AXI Ethernet Example DesignMore infoGit repoDocs
Processorless Example DesignMore infoGit repoDocs
Mates withVADJBuy
Ethernet FMC 1.8V1.8VOP031-1V8
Robust Ethernet FMC 1.8V1.8VOP041-1V8

See note 2 for more information regarding the VADJ options.

Connectors

  • HPC: Satisfies all of the Ethernet FMC requirements.
  • FMC+: Satisfies all of the Ethernet FMC requirements.

HTG-840

Mates withVADJBuy
Ethernet FMC 1.8V1.8VOP031-1V8
Robust Ethernet FMC 1.8V1.8VOP041-1V8

See note 2 for more information regarding the VADJ options.

Example designs

No example designs are currently available for this development board.

Connectors

  • HPC: Satisfies all of the Ethernet FMC requirements.

Arria 10 Attila

Mates withVADJBuy
Robust Ethernet FMC 1.8V1.8VOP041-1V8

Example designs

No example designs are currently available for this development board. Please contact REFLEX CES for support with this carrier.

Connectors

  • HPC: Satisfies all of the Ethernet FMC requirements.

TEBF0808

Example Designs
PS GEM Example DesignMore infoGit repoDocs
Mates withVADJBuy
Robust Ethernet FMC 1.8V1.8VOP041-1V8

See note 2 for more information regarding the VADJ options.

Configuration

DIP switch S5 must be properly configured for correct boot and VADJ voltage. Use one of the following settings depending on your desired boot mode.

DIP Switch S5

1234Boot mode
ONONxONSD/microSD or flash if no SD detected
OFFONxONeMMC
ONOFFxONPJTAG0
OFFOFFxONMain JTAG
  1. S5-3: Don’t care - is user defined (by CPLD)
  2. S5-4: Must be ON for FMC_VADJ 1.8V (OFF sets FMC_VADJ to 1.2V which is not supported by Ethernet FMC)

General board notes

  • The TEBF0808 requires a modified FSBL to setup clocks on the board before the bitstream is loaded and the application/OS is launched. The modifications are included in the example design repository and they are also described on the Trenz Wiki for the TE0808 StarterKit.

Mercury PE1-400 Base Board

When using Mercury XU1 module

Mates withVADJBuy
Ethernet FMC 1.8V1.8VOP031-1V8
Robust Ethernet FMC 1.8V1.8VOP041-1V8

See note 2 for more information regarding the VADJ options.

Example designs

No example designs are currently available for this development board. You can however download the pin constraints below:

Connectors

  • FMC0 (LPC): Satisfies all of the Ethernet FMC requirements.
  • FMC1 (LPC): Satisfies all of the Ethernet FMC requirements.

Footnotes


  1. We recommend using the 2.5V version on this board however it can support the 1.8V version with limitation. The FMC connector on this development board connects to HR (high-range) I/Os on the FPGA. Although HR I/Os can support many different I/O standards at 1.8V and 2.5V, when it comes to LVDS they only support the LVDS_25 standard which is designed for 2.5V. LVDS is required to receive the Ethernet FMC’s 125MHz clock. For this reason, we recommend using the 2.5V version Ethernet FMC with all development boards whose FMC connector is linked to HR I/Os. If you must use the 1.8V Ethernet FMC on one of these boards, do not use the 125MHz clock in your FPGA design and instead use a local clock source with sufficient precision for Gigabit Ethernet. ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎

  2. The device on this development board only has HP (high-performance) I/Os that don’t support 2.5V levels. This board can therefore only support the 1.8V version Ethernet FMC. because they only have HP (high-performance) I/Os that don’t support 2.5V levels. ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎

  3. The ML605 has a fixed VADJ of 2.5V. ↩︎