Programming Guide

This section provides the details of the programming requirements to operate the Ethernet FMC hardware and customise functionality.

PHY registers

For correct operation of the Ethernet FMC, the 4x Marvell Gigabit Ethernet PHYs must be properly configured over the MDIO bus (for more information, see PHY Configuration). The Marvell PHYs have registers that control the operation and functionality of the device and the Ethernet link. The registers have default values that are applied when the PHY is powered up and released from reset. The default register values are suitable for a wide range of use cases, but some of them you might want to change to suit your application.

The tables below list some of the registers and settings that are useful for basic operation of the Ethernet FMC. For a comprehensive list of the registers, please refer to the Marvell Marvell 88E151x public datasheet .

Copper Control Register, Copper Control Reg, Page 0, Reg 0

BitsDescriptionModeDefault Value
15Copper software resetR/W, SC0x0
12Enable Auto-negotiationR/W0x1
9Restart Auto-negotiationR/W, SC0x0

Copper Status Register, Copper Status Reg, Page 0, Reg 1

BitsDescriptionModeDefault Value
5Auto-negotiation CompleteRO0x0

Copper Auto-Negotiation Advertisement Register, Copper Auto-Neg Advertisement Reg, Page 0, Reg 4

BitsDescriptionModeDefault Value
11Asymmetric pauseR/W0x0
10MAC pauseR/W0x0
8Advertise 100Mbps full duplexR/W0x1
7Advertise 100Mbps half duplexR/W0x1
6Advertise 10Mbps full duplexR/W0x1
5Advertise 10Mbps half duplexR/W0x1

1000BASE-T Control Register, 1000BASE-T Control Reg, Page 0, Reg 9

BitsDescriptionModeDefault Value
9Advertise 1Gbps full duplexR/W0x1
8Advertise 1Gbps half duplexR/W0x1

Copper Specific Status Register 1, Copper Specific Status Reg 1, Page 0, Reg 17

BitsDescriptionModeDefault Value
15:14Established link speed
Valid only when speed and duplex resolved asserted (bit 11)
10b = 1Gbps
01b = 100Mbps
00b = 10Mbps		RO0x2
11Speed and duplex resolvedRO0x0

Copper Interrupt Status Register, Copper Status Reg, Page 0, Reg 19

BitsDescriptionModeDefault Value
15Auto-negotiation ErrorRO, LH0x0

Page Address, Page Address Any Page, Reg 22

When accessing registers, we must set the page address register to the value of the page that is being targetted. For example, when accessing the MAC Specific Control Reg 2 (MAC Specific Control Reg 2, Page 2, Reg 21), we must first set the page address register (register 22) to 2 prior to performing the register access.

BitsDescriptionModeDefault Value
7:0For changing the Page AddressR/W0x00

MAC Specific Control Reg 2, MAC Specific Control Reg 2, Page 2, Reg 21

BitsDescriptionModeDefault Value
5RGMII Rx Timing Control
1 = Rx clock transitions when data stable
0 = Rx clock transitions when data transitions		R/W0x1
4RGMII Tx Timing Control
1 = Tx clock delay enabled in PHY
0 = Tx clock delay disabled in PHY		R/W0x1

Autonegotiation

After a hardware reset, the PHYs are configured by default to auto-negotiate with the link partner and advertise all possible link capabilities (1Gbps, 100Mbps, 10Mbps, full and half duplex). If desired, we can setup and initiate the auto-negotiation process manually through the PHY registers. One suggested method for doing this is illustrated by the following pseudocode:

  1. Set Page Address Any Page, Reg 22 to 0

  2. Read value of Copper Auto-Neg Advertisement Reg, Page 0, Reg 4

    • Enable asymmetric pause (assert bit 11)
    • Enable MAC pause (assert bit 10)
    • Advertise 100Mbps, 10Mbps, full and half duplex (assert bits 8,7,6 and 5)

  3. Write new value to Copper Auto-Neg Advertisement Reg, Page 0, Reg 4

  4. Read value of 1000BASE-T Control Reg, Page 0, Reg 9

    • Advertise 1Gbps full and half duplex (assert bits 9 and 8)

  5. Write new value to 1000BASE-T Control Reg, Page 0, Reg 9

  6. Read value of Copper Control Reg, Page 0, Reg 0

    • Enable auto-negotiation (assert bit 12)
    • Restart auto-negotiation process (assert bit 9)

  7. Write new value to Copper Control Reg, Page 0, Reg 0

  8. Read value of Copper Control Reg, Page 0, Reg 0

    • Trigger software reset (assert bit 15)

  9. Write new value to Copper Control Reg, Page 0, Reg 0

  10. Check the value of Copper Control Reg, Page 0, Reg 0 until software reset (bit 15) is deasserted

  11. Read value of Copper Status Reg, Page 0, Reg 1

  12. If auto-negotiation NOT complete (bit 5 deasserted) then

  1. Read value of Copper Specific Status Reg 1, Page 0, Reg 17 to determine link speed from bits 15:14

RGMII timing

As described in RGMII Interface Timing Considerations, the RGMII RX and TX clock skews must be appropriately configured in the PHY for proper operation of the Ethernet FMC. By default, both the RX and TX clock skews are enabled in the PHY, however when using the AMD Xilinx AXI Ethernet Subsystem IP , the TX clock skew must be disabled. The following pseudocode illustrates how to disable the TX clock skew, while leaving the RX clock skew enabled:

  1. Set Page Address Any Page, Reg 22 to 2

  2. Read value of MAC Specific Control Reg 2, Page 2, Reg 21

    • Disable TX clock delay (deassert bit 4)
    • Enable RX clock delay (assert bit 5)

  3. Write new value to MAC Specific Control Reg 2, Page 2, Reg 21

Note that when using the PS GEM with the GMII-to-RGMII converter IP, both TX and RX clock delays must be enabled in the PHY (the default configuration). Ensure however that the “TX clock skew added by PHY” option is enabled in that IP.

Processorless design

If you wish to use the Ethernet FMC in a processorless design (ie. without a processor to setup the PHYs or perform packet handling), then we suggest you start with our processorless example design:

You can also read more about the topic in this three part blog:

  1. Driving Ethernet Ports without a processor
  2. Processorless Ethernet: Part 2
  3. Processorless Ethernet: Part 3
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