Getting Started Guide

1. Choose an example design

The example designs, provided here, make it easy to get started with the Ethernet FMC on a number of different FPGA development boards. Get started by choosing an example design and clicking through to the source code.

2. Download the source code

Each example design is hosted in a separate repository (or “repo”) on Github. If you’re a Git user, simply clone the repo to your hard drive; if not, download the repo as a zip file and extract the contents to a directory on your hard drive. From now on, we refer to the source files on your hard drive as “the repo”.

3. Build the Vivado project for your hardware

The repo will contain a Vivado directory, that contains scripts for generating a Vivado project for a particular hardware platform (for example, the ZedBoard). To generate a Vivado project for your hardware platform, double click on the build batch file (.bat) that is named after your hardware. For example, if you are using the ZedBoard, the appropriate batch file would be “build-zedboard.bat”. The Vivado project will be generated automatically, and once the script has completed, you will find a new folder containing the Vivado project.

4. Open the project in Vivado

Run Vivado and open the project that you generated in the previous step. Then click on the Generate bitstream option to launch synthesis and implementation, and to create a bitstream for the project. Once the bistream generation has completed, export the project to the SDK by using the option File->Export->Export Hardware. Make sure that you tick “Include bitstream” and select “Local to project”.

5. Generate the SDK workspace

The repo will contain an SDK directory, that contains a script for generating the SDK workspace. It is important to generate the SDK workspace using this script and NOT using the Launch SDK option from Vivado. Run the SDK build script by double-clicking on the build-sdk.bat batch file. The generated workspace will contain the hardware definition files from your Vivado project, and the example software application.

6. Open the workspace in Xilinx SDK

Run Xilinx SDK from the Start menu and NOT from the Launch SDK option of Vivado. The SDK will ask you to select the workspace to open; you must select the SDK directory in the repo. Now select Project->Build automatically from the menu and allow the SDK to build the sources.

7. Setup your hardware

Connect the Ethernet FMC to your FPGA development board, as well as the cables for JTAG programming and UART
connection. Then power up the hardware. Find your hardware’s UART port in the Device Manager and then open a
terminal window in Putty or Teraterm using the appropriate comport and the settings: 115200 bps, 8 data bits, no parity, 1 stop bit.

8. Run the application in Xilinx SDK

In the SDK, select Xilinx Tools->Program FPGA to download the bitstream to the FPGA. Right-click on the application and select Run As->Launch on Hardware (System Debugger) to download and launch the application on the hardware.